This invention relates to a semiconductor integrated circuit and, more particularly, it relates to a large scale integrated circuit (LSI) comprising an internal voltage generating circuit for generating an internal potential lower than an externally applied voltage within the semiconductor chip and using the internal voltage as operating voltage of the semiconductor chip. Such a semiconductor integrated circuit is suitably used for a dynamic random access memory (DRAM).
In the current tide of an ever increasing demand for more power saving LSIs, massive efforts are being paid for optimizing the dimensions and the logic of the circuit. In the field of DRAMs, there has been developed a technology of arranging a step-down circuit (a circuit for generating a voltage lower than an externally applied voltage by means of the externally applied voltage) on a semiconductor chip and using the output voltage of the step-down circuit as voltage for operating the semiconductor chip in order to reduce the charging/discharging current of the circuit and hence save the power consumption of the circuit. This technology has effectively been used for 16M DRAMs.
The use of a step-down circuit would not be necessary, if the semiconductor chip per se could be driven by a lower operating voltage supplied from an external voltage source. However, currently available technologies do not allow the use of a low externally applied voltage due to the system to which the semiconductor chip is applied, the components installed on the substrate of the semiconductor chip and other factors. The only possible way of reducing the power consumption rate of a semiconductor chip at present seems to be the use of a step-down circuit arranged within the chip.
FIG. 1 of the accompanying drawings is a schematic circuit diagram of a known step-down circuit.
Referring to FIG. 1, the step-down circuit comprises an N-channel MOS transistor (NMOS transistor) TN having its drain connected to an externally applied voltage Vext to step down the Vext and its gate connected to a stepped up potential VPPI for generating an stepped down internal potential, the voltage of the source of the transistor being used as stepped down potential Vint.
The voltage of the node connected to the gate of the NMOS transistor TN is stepped up for the following reasons.
(1) There occurs a fall of potential equal to a threshold value Vth due to the operating characteristic of the NMOS transistor TN and hence the gate voltage is stepped up to compensate the fall to make the Vint operable as internal voltage.
(2) When the semiconductor chip is activated, its internal circuit is electrically charged and then discharged to consequently lower the voltage level of Vint that is used as power source voltage of the chip and, therefore, the Vint has to be raised to an intended level because the circuit cannot operate properly with such a lowered level of Vint. Since the electric charge and discharge cycle of the internal circuit takes place as a result of a series of circuit operations, the fall in the voltage of Vint has to be compensated quickly and hence said gate voltage is stepped up for this compensation on the part of Vint.
A step-down circuit of the type under consideration is normally very large and has a circuit size (corresponding to the channel width of the NMOS transistor TN of the circuit) of several centimeters, although the size may vary depending on the power consumption level of the chip. The large step-down circuit is typically divided into several parts that are arranged within the semiconductor chip as shown in FIG. 2.
In FIG. 2, reference numeral 91 denotes a DRAM chip and reference numeral 92 denotes a memory cell array, whereas reference numeral 93 denotes a step-down circuit.
An NMOS transistor TN to be used in a step-down circuit as described above is normally also divided into unit NMOS transistors Tr having identical dimensions taking the possible gate delay into consideration, whose equivalent circuits and pattern layout are shown in FIGS. 3A and 3B respectively.
As shown in FIG. 4, an NMOS transistor TN to be used in a step-down circuit is not completely turned off when the voltage of the source rises to a certain level because it keeps on operating in a weak inversion zone to allow an electric current to flow therethrough and the source voltage Vint to gradually rise with time until Vint finally gets to the level of the drain voltage Vext (the rise in the Vint being indicated by DV in FIG. 4).
However, a DRAM chip can operate in any of several different modes where Vint dose not operates for a long period of time. Assume a mode of operation where external input signal /RAS has a long precharge time. The DRAM chip starts to become precharged when the signal /RAS moves from an active state (level "L") into an inactive state (level "H") and the precharging operation terminates after a certain period of time, when the operation of discharging the internal circuit of the DRAM also terminates.
Note that, however, the /RAS remains in the precharging conditions after the chip has been precharged to a necessary level if the precharging time is too long, although the chip does not operate according to the /RAS so that the Vint would not be subjected to charging and discharging and hence its voltage level rises.
FIG. 5 shows an external signal input circuit (e.g., a /RAS input buffer circuit) where problems can arise when the Vint rises above a preselected voltage.
FIG. 6A illustrates the relationship between the input voltage VIN and the output voltage VOUT (input/output characteristic) of the external signal input circuit of FIG. 5 when the operating voltage is equal to Vint and when it is equal to Vext.
The curves of the input/output characteristic of the input circuit has respective threshold values where the VOUT dramatically changes relative to the change in the value of VIN and the threshold value is shifted from a lower Vth1 to a higher Vth2 when the operating voltage of the input circuit is raised.
If the circuit threshold value is shifted from Vth1=0.7 V to Vth2=1.0 V, the following problem appears.
As the VIN is raised from 0 V with an operating voltage of the circuit equal to Vint, the VOUT shows a dramatic change at VIN=0.7 V and falls to 0 V at VIN=0.9 V. However, if the operating voltage is Vext, VOUT=Vext at VIN=0.7 and the VOUT is held to level "H" when the VIN is raised to 0.9 V. In other words, the level "H" of the input voltage is equal to 0.7 when the operating voltage is Vint, whereas the operating voltage does not exceed level "H" of the input voltage when the operating voltage is shifted to Vext and VIN=0.7 V so that the input voltage is judged to be at level "L" and the VOUT is not inverted (operational failure).
If the circuit is driven at a voltage higher than Vint, then the power consumption rate rises as a matter of course. Since all the circuits other than the external signal input circuit that are driven by Vint also consume power at an enhanced rate, the overall power consumption rate of the internal circuit would be enormous.
A technique of connecting a MOS transistor to a bleeder resistor is known from various existing documents including Japanese Patent Application KOKAI Publication No. 7-36557. However, it is a technique of connecting a resistor between the drain of a PMOS transistor to which the output voltage Vint of an internal step-down circuit is applied and a grounding node and hence not effective for suppressing the possible rise in the Vint.